NXP Semiconductors KL25 Series - Timer Load Value Register (Pit_Ldvaln)

32.3.4 Timer Load Value Register (PIT_LDVALn)
These registers select the timeout period for the timer interrupts.
Address: 4003_7000h base + 100h offset + (16d × i), where i=0d to 1d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
TSV
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIT_LDVALn field descriptions
Field Description
0–31
TSV
Timer Start Value
Sets the timer start value. The timer will count down until it reaches 0, then it will generate an interrupt and
load this register value again. Writing a new value to this register will not restart the timer; instead the
value will be loaded after the timer expires. To abort the current cycle and start a timer period with the new
value, the timer must be disabled and enabled again.
32.3.5 Current Timer Value Register (PIT_CVALn)
These registers indicate the current timer position.
Address: 4003_7000h base + 104h offset + (16d × i), where i=0d to 1d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
TVL
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIT_CVALn field descriptions
Field Description
0–31
TVL
Current Timer Value
Represents the current timer value, if the timer is enabled.
NOTE: • If the timer is disabled, do not use this field as its value is unreliable.
• The timer uses a downcounter. The timer values are frozen in Debug mode if MCR[FRZ] is
set.
Memory map/register description
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
578 Freescale Semiconductor, Inc.