NXP Semiconductors KL25 Series - USB Control Register (Usbx_Usbctrl)

In Host mode ENDPT0 is used to determine the handshake, retry and low speed
characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the
EPHSHK bit should be 1. For Isochronous transfers it should be 0. Common values to
use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers, and
0x4C for Isochronous transfers.
Address: 4007_2000h base + C0h offset + (4d × i), where i=0d to 15d
Bit 7 6 5 4 3 2 1 0
Read HOSTWOH
UB
RETRYDIS
0
EPCTLDIS EPRXEN EPTXEN EPSTALL EPHSHK
Write
Reset
0 0 0 0 0 0 0 0
USBx_ENDPTn field descriptions
Field Description
7
HOSTWOHUB
This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only. When
set this bit allows the host to communicate to a directly connected low speed device. When cleared, the
host produces the PRE_PID. It then switches to low-speed signaling when sends a token to a low speed
device as required to communicate with a low speed device through a hub.
6
RETRYDIS
This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only. When set
this bit causes the host to not retry NAK'ed (Negative Acknowledgement) transactions. When a transaction
is NAKed, the BDT PID field is updated with the NAK PID, and the TOKEN_DNE interrupt is set. When
this bit is cleared NAKed transactions is retried in hardware. This bit must be set when the host is
attempting to poll an interrupt endpoint.
5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
4
EPCTLDIS
This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This
applies if and only if the EPRXEN and EPTXEN bits are also set.
3
EPRXEN
This bit, when set, enables the endpoint for RX transfers.
2
EPTXEN
This bit, when set, enables the endpoint for TX transfers.
1
EPSTALL
When set this bit indicates that the endpoint is called. This bit has priority over all other control bits in the
EndPoint Enable Register, but it is only valid if EPTXEN=1 or EPRXEN=1. Any access to this endpoint
causes the USB Module to return a STALL handshake. After an endpoint is stalled it requires intervention
from the Host Controller.
0
EPHSHK
When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint. This
bit is generally 1 unless the endpoint is Isochronous.
35.4.24 USB Control register (USBx_USBCTRL)
Address: 4007_2000h base + 100h offset = 4007_2100h
Bit 7 6 5 4 3 2 1 0
Read
SUSP PDE
0
Write
Reset
1 1 0 0 0 0 0 0
Memory map/Register definitions
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
640 Freescale Semiconductor, Inc.