Table 3-23. COP configuration options (continued)
Control Bits Clock Source COP Window Opens
(COPCTRL[COPW]=1)
COP Overflow Count
COPCTRL[COPCLKS] COPCTRL[COPT]
0 10 1 kHz N/A 2
8
cycles (256 ms)
0 11 1 kHz N/A 2
10
cycles (1024 ms)
1 01 Bus 6,144 cycles 2
13
cycles
1 10 Bus 49,152 cycles 2
16
cycles
1 11 Bus 196,608 cycles 2
18
cycles
After the bus clock source is selected, windowed COP operation is available by setting
COPCTRL[COPW] in the SIM. In this mode, writes to the SRVCOP register to clear the
COP timer must occur in the last 25% of the selected timeout period. A premature write
immediately resets the chip. When the 1 kHz clock source is selected, windowed COP
operation is not available.
The COP counter is initialized by the first writes to the SIM's COPCTRL register and
after any system reset. Subsequent writes to the SIM's COPCTRL register have no effect
on COP operation. Even if an application uses the reset default settings of the COPT,
COPCLKS, and COPW bits, the user should write to the write-once COPCTRL register
during reset initialization to lock in the settings. This approach prevents accidental
changes if the application program becomes lost.
The write to the SRVCOP register that services (clears) the COP counter should not be
placed in an interrupt service routine (ISR) because the ISR could continue to be
executed periodically even if the main application program fails.
If the bus clock source is selected, the COP counter does not increment while the
microcontroller is in debug mode or while the system is in stop (including VLPS or LLS)
mode. The COP counter resumes when the microcontroller exits debug mode or stop
mode.
If the 1 kHz clock source is selected, the COP counter is re-initialized to zero upon entry
to either debug mode or stop (including VLPS or LLS) mode. The counter begins from
zero upon exit from debug mode or stop mode.
Regardless of the clock selected, the COP is disabled when the chip enters a VLLSx
mode. Upon a reset that wakes the chip from the VLLSx mode, the COP is re-initialized
and enabled as for any reset.
Chapter 3 Chip Configuration
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 69
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