NXP Semiconductors KL25 Series - I2 C Data I;O Register (I2 Cx_D)

I2Cx_S field descriptions (continued)
Field Description
• Any nonzero calling address is received that matches the address in the RA register.
• The RMEN bit is set and the calling address is within the range of values of the A1 and RA registers.
NOTE: For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1.
Writing the C1 register with any value clears this bit to 0.
0 Not addressed
1 Addressed as a slave
2
SRW
Slave Read/Write
When addressed as a slave, SRW indicates the value of the R/W command bit of the calling address sent
to the master.
0 Slave receive, master writing to slave
1 Slave transmit, master reading from slave
1
IICIF
Interrupt Flag
This bit sets when an interrupt is pending. This bit must be cleared by software by writing a 1 to it, such as
in the interrupt routine. One of the following events can set this bit:
• One byte transfer, including ACK/NACK bit, completes if FACK is 0. An ACK or NACK is sent on the
bus by writing 0 or 1 to TXAK after this bit is set in receive mode.
• One byte transfer, excluding ACK/NACK bit, completes if FACK is 1.
• Match of slave address to calling address including primary slave address, range slave address,
alert response address, second slave address, or general call address.
• Arbitration lost
• In SMBus mode, any timeouts except SCL and SDA high timeouts
• I2C bus stop detection if the STOPIE bit in the Input Glitch Filter register is 1
NOTE: To clear the I2C bus stop detection interrupt: In the interrupt service routine,
first clear the STOPF bit in the Input Glitch Filter register by writing 1 to it, and
then clear the IICIF bit. If this sequence is reversed, the IICIF bit is asserted
again.
0 No interrupt pending
1 Interrupt pending
0
RXAK
Receive Acknowledge
0 Acknowledge signal was received after the completion of one byte of data transmission on the bus
1 No acknowledge signal detected
38.3.5 I2C Data I/O register (I2Cx_D)
Address: Base address + 4h offset
Bit 7 6 5 4 3 2 1 0
Read
DATA
Write
Reset
0 0 0 0 0 0 0 0
Chapter 38 Inter-Integrated Circuit (I2C)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 695