I2Cx_FLT field descriptions (continued)
Field Description
If the SHEN bit is set to 1 and the I2C module is in an idle or disabled state when the MCU signals to enter
stop mode, the module immediately acknowledges the request to enter stop mode.
If SHEN is cleared to 0 and the overall data transmission or reception that was suspended by stop mode
entry was incomplete: To resume the overall transmission or reception after the MCU exits stop mode,
software must reinitialize the transfer by resending the address of the slave.
If the I2C Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode, system software
will receive the interrupt triggered by the I2C Status Register's TCF bit after the MCU wakes from the stop
mode.
0 Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
1 Stop holdoff is enabled.
6
STOPF
I2C Bus Stop Detect Flag
Hardware sets this bit when the I2C bus's stop status is detected. The STOPF bit must be cleared by
writing 1 to it.
0 No stop happens on I2C bus
1 Stop detected on I2C bus
5
STOPIE
I2C Bus Stop Interrupt Enable
This bit enables the interrupt for I2C bus stop detection.
NOTE: To clear the I2C bus stop detection interrupt: In the interrupt service routine, first clear the STOPF
bit by writing 1 to it, and then clear the IICIF bit in the status register. If this sequence is reversed,
the IICIF bit is asserted again.
0 Stop detection interrupt is disabled
1 Stop detection interrupt is enabled
4–0
FLT
I2C Programmable Filter Factor
Controls the width of the glitch, in terms of bus clock cycles, that the filter must absorb. For any glitch
whose size is less than or equal to this width setting, the filter does not allow the glitch to pass.
00h No filter/bypass
01-1Fh Filter glitches up to width of n bus clock cycles, where n=1-31d
38.3.8 I2C Range Address register (I2Cx_RA)
Address: Base address + 7h offset
Bit 7 6 5 4 3 2 1 0
Read
RAD
0
Write
Reset
0 0 0 0 0 0 0 0
I2Cx_RA field descriptions
Field Description
7–1
RAD
Range Slave Address
Table continues on the next page...
Memory map and register descriptions
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
698 Freescale Semiconductor, Inc.
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