NXP Semiconductors KL25 Series - UART Match Address Registers 1 (Uartx_Ma1)

UARTx_D field descriptions (continued)
Field Description
4
R4T4
Read receive data buffer 4 or write transmit data buffer 4.
3
R3T3
Read receive data buffer 3 or write transmit data buffer 3.
2
R2T2
Read receive data buffer 2 or write transmit data buffer 2.
1
R1T1
Read receive data buffer 1 or write transmit data buffer 1.
0
R0T0
Read receive data buffer 0 or write transmit data buffer 0.
39.2.9 UART Match Address Registers 1 (UARTx_MA1)
The MA1 and MA2 registers are compared to input data addresses when the most
significant bit is set and the associated C4[MAEN] bit is set. If a match occurs, the
following data is transferred to the data register. If a match fails, the following data is
discarded. Software should only write a MA register when the associated C4[MAEN] bit
is clear.
Address: Base address + 8h offset
Bit 7 6 5 4 3 2 1 0
Read
MA
Write
Reset
0 0 0 0 0 0 0 0
UARTx_MA1 field descriptions
Field Description
7–0
MA
Match Address
Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 735