NXP Semiconductors KL25 Series - UART Control Register 1 (Uartx_C1)

UART_BDL is reset to a non-zero value, so after reset the baud rate generator remains
disabled until the first time the receiver or transmitter is enabled; that is, UART_C2[RE]
or UART_C2[TE] bits are written to 1.
Address: Base address + h offset
Bit 7 6 5 4 3 2 1 0
Read
SBR
Write
Reset
0 0 0 0 0 1 0 0
UARTx_BDL field descriptions
Field Description
7–0
SBR
Baud Rate Modulo Divisor
These 13 bits in SBR[12:0] are referred to collectively as BR. They set the modulo divide rate for the
UART baud rate generator. When BR is cleared, the UART baud rate generator is disabled to reduce
supply current. When BR is 1 - 8191, the UART baud rate equals BUSCLK/(16×BR).
40.2.3 UART Control Register 1 (UARTx_C1)
This read/write register controls various optional features of the UART system.
Address: Base address + h offset
Bit 7 6 5 4 3 2 1 0
Read
LOOPS UARTSWAI RSRC M WAKE ILT PE PT
Write
Reset
0 0 0 0 0 0 0 0
UARTx_C1 field descriptions
Field Description
7
LOOPS
Loop Mode Select
Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS is set, the
transmitter output is internally connected to the receiver input.
0 Normal operation - RxD and TxD use separate pins.
1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input.
(See RSRC bit.) RxD pin is not used by UART.
6
UARTSWAI
UART Stops in Wait Mode
0 UART clocks continue to run in wait mode so the UART can be the source of an interrupt that wakes
up the CPU.
1 UART clocks freeze while CPU is in wait mode.
5
RSRC
Receiver Source Select
Table continues on the next page...
Register definition
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
752 Freescale Semiconductor, Inc.