NXP Semiconductors KL25 Series - Port Data Direction Register (Gpiox_Pddr)

41.2.6 Port Data Direction Register (GPIOx_PDDR)
The PDDR configures the individual port pins for input or output.
Address: Base address + 14h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PDD
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_PDDR field descriptions
Field Description
31–0
PDD
Port Data Direction
Configures individual port pins for input or output.
0 Pin is configured as general-purpose input, for the GPIO function.
1 Pin is configured as general-purpose output, for the GPIO function.
41.3 FGPIO memory map and register definition
Any read or write access to the FGPIO memory space that is outside the valid memory
map results in a bus error. All register accesses complete with zero wait states, except
error accesses which complete with one wait state.
NOTE
For simplicity, each FGPIO port's registers appear with the
same width of 32 bits, corresponding to 32 pins. The actual
number of pins per port (and therefore the number of usable
control bits per port register) is chip-specific. Refer to the Chip
Configuration chapter to see the exact control bits for the non-
identical port instance.
FGPIO memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
F80F_F000 Port Data Output Register (FGPIOA_PDOR) 32 R/W 0000_0000h 41.3.1/780
F80F_F004 Port Set Output Register (FGPIOA_PSOR) 32
W
(always
reads 0)
0000_0000h 41.3.2/781
Table continues on the next page...
FGPIO memory map and register definition
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
778 Freescale Semiconductor, Inc.