The CMP does not support window compare function and CMP_CR1[WE] must always
be written to 0. The sample function has limited functionality since the SAMPLE input to
the block is not connected to a valid input. Usage of sample operation is limited to a
divided version of the bus clock (CMP_CR1[SE] = 0).
Due to the pin number limitation, the CMP pass through mode is not supported by this
device, so the CMPx_MUXCR[PSTM] must be left as 0.
3.7.2.2 CMP input connections
The following table shows the fixed internal connections to the CMP.
Table 3-34. CMP input connections
CMP Inputs CMP0
IN0 CMP0_IN0
IN1 CMP0_IN1
IN2 CMP0_IN2
IN3 CMP0_IN3
IN4 12-bit DAC0 reference/ CMP0_IN4
IN5 CMP0_IN5
IN6 Bandgap
1
IN7 6-bit DAC0 reference
1. This is the PMC bandgap 1V reference voltage. Prior to using as CMP input, ensure that you enable the bandgap buffer by
setting the PMC_REGSC[BGBE] bit. Refer to the device data sheet for the bandgap voltage (V
BG
) specification.
3.7.2.3 CMP external references
The 6-bit DAC sub-block supports selection of two references. For this device, the
references are connected as follows:
• VREFH - V
in1
input. When using VREFH, any ADC conversion using this same
reference at the same time is negatively impacted.
• VDD - V
in2
input
3.7.2.4 CMP trigger mode
The CMP and 6-bit DAC sub-block supports trigger mode operation when the
CMP_CR1[TRIGM] is set. When trigger mode is enabled, the trigger event will initiate a
compare sequence that must first enable the CMP and DAC prior to performing a CMP
operation and capturing the output. In this device, control for this two staged sequencing
Analog
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
82 Freescale Semiconductor, Inc.
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