NXP Semiconductors MC9S12G - Page 133

Device Overview MC9S12G-Family
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 135
57 PAD1 KWAD1 AN1 — V
DDA
PER1AD/PPS1AD Disabled
58 PAD9 KWAD9 AN9 — V
DDA
PER0AD/PPS0AD Disabled
59 PAD2 KWAD2 AN2 — V
DDA
PER1AD/PPS1AD Disabled
60 PAD10 KWAD10 AN10 AMP1 V
DDA
PER0AD/PPS0AD Disabled
61 PAD3 KWAD3 AN3 — V
DDA
PER1AD/PPS1AD Disabled
62 PAD11 KWAD11 AN11 AMP0 V
DDA
PER0AD/PPS0AD Disabled
63 PAD4 KWAD4 AN4 — V
DDA
PER1AD/PPS1AD Disabled
64 PAD12 KWAD12 AN12 — V
DDA
PER0AD/PPS0AD Disabled
65 PAD5 KWAD5 AN5 — V
DDA
PER1AD/PPS1AD Disabled
66 PAD13 KWAD13 AN13 AMPM0 V
DDA
PER0AD/PPS0AD Disabled
67 PAD6 KWAD6 AN6 — V
DDA
PER1AD/PPS1AD Disabled
68 PAD14 KWAD14 AN14 AMPP0 V
DDA
PER0AD/PPS0AD Disabled
69 PAD7 KWAD7 AN7 — V
DDA
PER1AD/PPS1AD Disabled
70 PAD15 KWAD15 AN15 DACU0 V
DDA
PER0AD/PPS0AD Disabled
71PC4———V
DDA
PUCR/PUPCE Disabled
72 PC5 AMPM1 — — V
DDA
PUCR/PUPCE Disabled
73 PC6 AMPP1 — — V
DDA
PUCR/PUPCE Disabled
74 PC7 DACU1 — — V
DDA
PUCR/PUPCE Disabled
75VRH———— — —
76VDDA———— — —
77 VSSA — — — — — —
78PD0———V
DDX
PUCR/PUPDE Disabled
79PD1———V
DDX
PUCR/PUPDE Disabled
80PD2———V
DDX
PUCR/PUPDE Disabled
81PD3———V
DDX
PUCR/PUPDE Disabled
82 PS0 RXD0 — — V
DDX
PERS/PPSS Up
83 PS1 TXD0 — — V
DDX
PERS/PPSS Up
84 PS2 RXD1 — — V
DDX
PERS/PPSS Up
85 PS3 TXD1 — — V
DDX
PERS/PPSS Up
Table 1-31. 100-Pin LQFP Pinout for S12GA192 and S12GA240
Function
<----lowest-----PRIORITY-----highest---->
Power
Supply
Internal Pull
Resistor
Package Pin Pin
2nd
Func.
3rd
Func.
4th
Func.
CTRL
Reset
State