NXP Semiconductors MC9S12G - Page 209

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 211
2.4.3.21 Port S Input Register (PTIS)
2.4.3.22 Port S Data Direction Register (DDRS)
Table 2-40. PTS Register Field Descriptions
Field Description
7-0
PTS
Port S general-purpose input/output data—Data Register
When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In general-purpose
output mode the port data register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read.
Address 0x0249 Access: User read only
1
1
Read: Anytime
Write:Never
76543210
R PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0
W
Reset00000000
Figure 2-22. Port S Input Register (PTIS)
Table 2-41. PTIS Register Field Descriptions
Field Description
7-0
PTIS
Port S input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Address 0x024A Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0
W
Reset00000000
Figure 2-23. Port S Data Direction Register (DDRS)