Table 7-1. Chip power modes (continued)
Chip mode Description Core mode Normal
recovery
method
VLLS1 (Very
Low Leakage
Stop1)
Most peripherals are disabled (with clocks stopped), but OSC, LLWU,
LPTMR, RTC, CMP, TSI can be used. NVIC is disabled; LLWU is used
to wake up.
All of SRAM_U and SRAM_L are powered off.
Sleep Deep Wakeup Reset
2
VLLS0 (Very
Low Leakage
Stop 0)
Most peripherals are disabled (with clocks stopped), but LLWU,
LPTMR, RTC, TSI can be used. NVIC is disabled; LLWU is used to
wake up.
All of SRAM_U and SRAM_L are powered off.
LPO disabled, optional POR brown-out detection
Sleep Deep Wakeup Reset
2
1. Resumes normal run mode operation by executing the LLWU interrupt service routine.
2. Follows the reset flow with the LLWU interrupt flag set for the NVIC.
7.4 Entering and exiting power modes
The WFI instruction invokes wait and stop modes for the chip. The processor exits the
low-power mode via an interrupt. For LLS and VLLS modes, the wakeup sources are
limited to LLWU generated wakeups, NMI pin, or RESET pin assertions. When the NMI
pin or RESET pin have been disabled through associated FOPT settings, then these pins
are ignored as wakeup sources. The wake-up flow from VLLSx is always through reset.
NOTE
The WFE instruction can have the side effect of entering a low-
power mode, but that is not its intended usage. See ARM
documentation for more on the WFE instruction.
On VLLS recoveries, the I/O pins continue to be held in a static state after code execution
begins, allowing software to reconfigure the system before unlocking the I/O. RAM is
retained in VLLS3 only.
7.5 Module Operation in Low Power Modes
The following table illustrates the functionality of each module while the chip is in each
of the low power modes. The standard behavior is shown with some exceptions for
Compute Operation (CPO) and Partial Stop2 (PSTOP2).
Chapter 7 Power Management
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 143
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