NXP Semiconductors MKL25Z128VLK4 - Page 162

80
LQFP
64
LQFP
48
QFN
32
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
3 — — — PTE2 DISABLED PTE2 SPI1_SCK
4 — — — PTE3 DISABLED PTE3 SPI1_MISO SPI1_MOSI
5 — — — PTE4 DISABLED PTE4 SPI1_PCS0
6 — — — PTE5 DISABLED PTE5
7 3 1 — VDD VDD VDD
8 4 2 2 VSS VSS VSS
9 5 3 3 USB0_DP USB0_DP USB0_DP
10 6 4 4 USB0_DM USB0_DM USB0_DM
11 7 5 5 VOUT33 VOUT33 VOUT33
12 8 6 6 VREGIN VREGIN VREGIN
13 9 7 — PTE20 ADC0_DP0/
ADC0_SE0
ADC0_DP0/
ADC0_SE0
PTE20 TPM1_CH0 UART0_TX
14 10 8 — PTE21 ADC0_DM0/
ADC0_SE4a
ADC0_DM0/
ADC0_SE4a
PTE21 TPM1_CH1 UART0_RX
15 11 — — PTE22 ADC0_DP3/
ADC0_SE3
ADC0_DP3/
ADC0_SE3
PTE22 TPM2_CH0 UART2_TX
16 12 — — PTE23 ADC0_DM3/
ADC0_SE7a
ADC0_DM3/
ADC0_SE7a
PTE23 TPM2_CH1 UART2_RX
17 13 9 7 VDDA VDDA VDDA
18 14 10 — VREFH VREFH VREFH
19 15 11 — VREFL VREFL VREFL
20 16 12 8 VSSA VSSA VSSA
21 17 13 — PTE29 CMP0_IN5/
ADC0_SE4b
CMP0_IN5/
ADC0_SE4b
PTE29 TPM0_CH2 TPM_CLKIN0
22 18 14 9 PTE30 DAC0_OUT/
ADC0_SE23/
CMP0_IN4
DAC0_OUT/
ADC0_SE23/
CMP0_IN4
PTE30 TPM0_CH3 TPM_CLKIN1
23 19 — — PTE31 DISABLED PTE31 TPM0_CH4
24 20 15 — PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL
25 21 16 — PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA
26 22 17 10 PTA0 SWD_CLK TSI0_CH1 PTA0 TPM0_CH5 SWD_CLK
27 23 18 11 PTA1 DISABLED TSI0_CH2 PTA1 UART0_RX TPM2_CH0
28 24 19 12 PTA2 DISABLED TSI0_CH3 PTA2 UART0_TX TPM2_CH1
29 25 20 13 PTA3 SWD_DIO TSI0_CH4 PTA3 I2C1_SCL TPM0_CH0 SWD_DIO
30 26 21 14 PTA4 NMI_b TSI0_CH5 PTA4 I2C1_SDA TPM0_CH1 NMI_b
31 27 — — PTA5 DISABLED PTA5 USB_CLKIN TPM0_CH2
32 28 — — PTA12 DISABLED PTA12 TPM1_CH0
33 29 — — PTA13 DISABLED PTA13 TPM1_CH1
34 — — — PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX
35 — — — PTA15 DISABLED PTA15 SPI0_SCK UART0_RX
36 — — — PTA16 DISABLED PTA16 SPI0_MOSI SPI0_MISO
37 — — — PTA17 DISABLED PTA17 SPI0_MISO SPI0_MOSI
38 30 22 15 VDD VDD VDD
Pinout
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
162 Freescale Semiconductor, Inc.