NXP Semiconductors MKL25Z128VLK4 - System Clock Divider Register 1 (SIM_CLKDIV1)

12.2.12 System Clock Divider Register 1 (SIM_CLKDIV1)
NOTE
The CLKDIV1 register cannot be written to when the device is
in VLPR mode.
NOTE
Reset value loaded during System Reset from
FTF_FOPT[LPBOOT].
Address: 4004_7000h base + 1044h offset = 4004_8044h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
OUTDIV1
0
OUTDIV4
0
W
Reset
* * * * 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
* Notes:
OUTDIV1 field: The reset value depends on the FTF_FOPT[LPBOOT]. it is loaded with 0000 (divide by one), 0001 (divide
by two), 0011 (divide by four), or 0111 (divide by eight).
•
SIM_CLKDIV1 field descriptions
Field Description
31–28
OUTDIV1
Clock 1 output divider value
This field sets the divide value for the core/system clock, as well as the bus/flash clocks. At the end of
reset, it is loaded with 0000 (divide by one), 0001 (divide by two), 0011 (divide by four), or 0111 (divide by
eight) depending on the setting of the two FTF_FOPT[LPBOOT] configuration bits.
0000 Divide-by-1.
0001 Divide-by-2.
0010 Divide-by-3.
0011 Divide-by-4.
0100 Divide-by-5.
0101 Divide-by-6.
0110 Divide-by-7.
0111 Divide-by-8.
1000 Divide-by-9.
1001 Divide-by-10.
1010 Divide-by-11.
1011 Divide-by-12.
1100 Divide-by-13.
1101 Divide-by-14.
1110 Divide-by-15.
1111 Divide-by-16.
27–19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Memory map and register definition
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
210 Freescale Semiconductor, Inc.