Table 13-7. Power mode transition triggers (continued)
Transition # From To Trigger conditions
2 RUN STOP PMCTRL[RUNM]=00, PMCTRL[STOPM]=000
2
Sleep-now or sleep-on-exit modes entered with SLEEPDEEP
set, which is controlled in System Control Register in ARM
core.
See note.
1
STOP RUN Interrupt or Reset
3 RUN VLPR The core, system, bus and flash clock frequencies are
restricted in this mode. See the Power Management chapter
for the maximum allowable frequencies.
Set PMPROT[AVLP]=1, PMCTRL[RUNM]=10.
VLPR RUN Set PMCTRL[RUNM]=00 or
Reset.
4 VLPR VLPW Sleep-now or sleep-on-exit modes entered with SLEEPDEEP
clear, which is controlled in System Control Register in ARM
core.
See note.
1
VLPW VLPR Interrupt
5 VLPW RUN Reset
6 VLPR VLPS PMCTRL[STOPM]=000
3
or 010,
Sleep-now or sleep-on-exit modes entered with SLEEPDEEP
set, which is controlled in System Control Register in ARM
core.
See note.
1
VLPS VLPR Interrupt
NOTE: If VLPS was entered directly from RUN, hardware
will not allow this transition and will force exit back to
RUN
7 RUN VLPS PMPROT[AVLP]=1, PMCTRL[STOPM]=010,
Sleep-now or sleep-on-exit modes entered with SLEEPDEEP
set, which is controlled in System Control Register in ARM
core.
See note.
1
VLPS RUN Interrupt and VLPS mode was entered directly from RUN or
Reset
8 RUN VLLSx PMPROT[AVLLS]=1, PMCTRL[STOPM]=100,
STOPCTRL[VLLSM]=x (VLLSx), Sleep-now or sleep-on-exit
modes entered with SLEEPDEEP set, which is controlled in
System Control Register in ARM core.
VLLSx RUN Wakeup from enabled LLWU input source or RESET pin
9 VLPR VLLSx PMPROT[AVLLS]=1, PMCTRL[STOPM]=100,
STOPCTRL[VLLSM]=x (VLLSx), Sleep-now or sleep-on-exit
modes entered with SLEEPDEEP set, which is controlled in
System Control Register in ARM core.
Table continues on the next page...
Functional description
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
226 Freescale Semiconductor, Inc.
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