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NXP Semiconductors MKL25Z128VLK4 - Initialization;Application Information; Reset; Enabling and Configuring Sources

NXP Semiconductors MKL25Z128VLK4
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By configuring the DMA to transfer all of the data in a single minor loop (that is,
major loop counter = 1), no reactivation of the channel is necessary. The
disadvantage to this option is the reduced granularity in determining the load that the
DMA transfer will impose on the system. For this option, the DMA channel must be
disabled in the DMA channel MUX.
Use explicit software reactivation.
In this option, the DMA is configured to transfer the data using both minor and major
loops, but the processor is required to reactivate the channel by writing to the DMA
registers after every minor loop. For this option, the DMA channel must be disabled
in the DMA channel MUX.
Use an always-enabled DMA source.
In this option, the DMA is configured to transfer the data using both minor and major
loops, and the DMA channel MUX does the channel reactivation. For this option, the
DMA channel should be enabled and pointing to an "always enabled" source. Note
that the reactivation of the channel can be continuous (DMA triggering is disabled)
or can use the DMA triggering capability. In this manner, it is possible to execute
periodic transfers of packets of data from one source to another, without processor
intervention.
22.5 Initialization/application information
This section provides instructions for initializing the DMA channel MUX.
22.5.1 Reset
The reset state of each individual bit is shown in Memory map/register definition. In
summary, after reset, all channels are disabled and must be explicitly enabled before use.
22.5.2 Enabling and configuring sources
To enable a source with periodic triggering:
1. Determine with which DMA channel the source will be associated. Note that only the
first 2 DMA channels have periodic triggering capability.
2. Clear the CHCFG[ENBL] and CHCFG[TRIG] fields of the DMA channel.
Initialization/application information
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
344 Freescale Semiconductor, Inc.

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