DMA_DSR_BCRn field descriptions
Field Description
31
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
30
CE
Configuration error
Any of the following conditions causes a configuration error:
• BCR, SAR, or DAR does not match the requested transfer size.
• A value greater than 0F_FFFFh is written to BCR.
• Bits 31-20 of SAR or DAR are written with a value other than one of the allowed values. See SAR
and DAR.
• SSIZE or DSIZE is set to an unsupported value.
• BCR equals 0 when the DMA receives a start condition.
CE is cleared at hardware reset or by writing a 1 to the DONE bit.
0 No configuration error exists.
1 A configuration error has occurred.
29
BES
Bus error on source
BES is cleared at hardware reset or by writing a 1 to the DONE bit.
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the read portion of a transfer.
28
BED
Bus error on destination
BED is cleared at hardware reset or by writing a 1 to the DONE bit.
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the write portion of a transfer.
27
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
26
REQ
Request
0 No request is pending or the channel is currently active. Cleared when the channel is selected.
1 The DMA channel has a transfer remaining and the channel is not selected.
25
BSY
Busy
0 DMA channel is inactive. Cleared when the DMA has finished the last transaction.
1 BSY is set the first time the channel is enabled after a transfer is initiated.
24
DONE
Transactions done
Set when all DMA controller transactions complete as determined by transfer count, or based on error
conditions. When BCR reaches zero, DONE is set when the final transfer completes successfully. DONE
can also be used to abort a transfer by resetting the status bits. When a transfer completes, software must
clear DONE before reprogramming the DMA.
0 DMA transfer is not yet complete. Writing a 0 has no effect.
1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an
interrupt service routine to clear the DMA interrupt and error bits.
23–0
BCR
This field contains the number of bytes yet to be transferred for a given block.
Restriction: BCR must be written with a value equal to or less than 0F_FFFFh. After being written with a
value in this range, bits 23-20 of BCR read back as 1110b. A write to BCR of a value
Table continues on the next page...
Memory Map and Registers
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
356 Freescale Semiconductor, Inc.
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