NXP Semiconductors MKL25Z128VLK4 - MCG Control 2 Register (MCG_C2)

24.3.2 MCG Control 2 Register (MCG_C2)
Address: 4006_4000h base + 1h offset = 4006_4001h
Bit 7 6 5 4 3 2 1 0
Read
LOCRE0
0
RANGE0 HGO0 EREFS0 LP IRCS
Write
Reset
1 0 0 0 0 0 0 0
MCG_C2 field descriptions
Field Description
7
LOCRE0
Loss of Clock Reset Enable
Determines whether an interrupt or a reset request is made following a loss of OSC0 external reference
clock. The LOCRE0 only has an affect when CME0 is set.
0 Interrupt request is generated on a loss of OSC0 external reference clock.
1 Generate a reset request on a loss of OSC0 external reference clock.
6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
5–4
RANGE0
Frequency Range Select
Selects the frequency range for the crystal oscillator or external clock source. See the Oscillator (OSC)
chapter for more details and the device data sheet for the frequency ranges used.
00 Encoding 0 — Low frequency range selected for the crystal oscillator .
01 Encoding 1 — High frequency range selected for the crystal oscillator .
1X Encoding 2 — Very high frequency range selected for the crystal oscillator .
3
HGO0
High Gain Oscillator Select
Controls the crystal oscillator mode of operation. See the Oscillator (OSC) chapter for more details.
0 Configure crystal oscillator for low-power operation.
1 Configure crystal oscillator for high-gain operation.
2
EREFS0
External Reference Select
Selects the source for the external reference clock. See the Oscillator (OSC) chapter for more details.
0 External reference clock requested.
1 Oscillator requested.
1
LP
Low Power Select
Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or PBE modes, setting this
bit to 1 will transition the MCG into BLPE mode; in FBI mode, setting this bit to 1 will transition the MCG
into BLPI mode. In any other MCG mode, LP bit has no affect.
0 FLL or PLL is not disabled in bypass modes.
1 FLL or PLL is disabled in bypass modes (lower power)
0
IRCS
Internal Reference Clock Select
Selects between the fast or slow internal reference clock source.
Table continues on the next page...
Chapter 24 Multipurpose Clock Generator (MCG)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 373