NXP Semiconductors MKL25Z128VLK4 - Channel (N) Status and Control (Tpmx_Cnsc)

31.3.4 Channel (n) Status and Control (TPMx_CnSC)
CnSC contains the channel-interrupt-status flag and control bits used to configure the
interrupt enable, channel configuration, and pin function. When switching from one
channel mode to a different channel mode, the channel must first be disabled and this
must be acknowledged in the LPTPM counter clock domain.
Table 31-34. Mode, Edge, and Level Selection
CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration
X 00 00 None Channel disabled
X 01/10/11 00 Software compare Pin not used for LPTPM
0 00 01 Input capture Capture on Rising Edge
Only
10 Capture on Falling
Edge Only
11 Capture on Rising or
Falling Edge
01 01 Output compare Toggle Output on
match
10 Clear Output on match
11 Set Output on match
10 10 Edge-aligned PWM High-true pulses (clear
Output on match, set
Output on reload)
X1 Low-true pulses (set
Output on match, clear
Output on reload)
11 10 Output compare Pulse Output low on
match
X1 Pulse Output high on
match
1 10 10 Center-aligned PWM High-true pulses (clear
Output on match-up,
set Output on match-
down)
X1 Low-true pulses (set
Output on match-up,
clear Output on match-
down)
Address: Base address + Ch offset + (8d × i), where i=0d to 5d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 31 Timer/PWM Module (TPM)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 555