31.4.9 DMA
The channel generates a DMA transfer request according to DMA and CHnIE bits (see
the following table).
Table 31-110. Channel DMA Transfer Request
DMA CHnIE Channel DMA Transfer Request Channel Interrupt
0 0 The channel DMA transfer request is not
generated.
The channel interrupt is not generated.
0 1 The channel DMA transfer request is not
generated.
The channel interrupt is generated if (CHnF = 1).
1 0 The channel DMA transfer request is generated if
(CHnF = 1).
The channel interrupt is not generated.
1 1 The channel DMA transfer request is generated if
(CHnF = 1).
The channel interrupt is generated if (CHnF = 1).
If DMA = 1, the CHnF bit can be cleared either by channel DMA transfer done or writing
a one to CHnF bit (see the following table).
Table 31-111. Clear CHnF Bit
DMA How CHnF Bit Can Be Cleared
0 CHnF bit is cleared by writing a 1 to CHnF bit.
1 CHnF bit is cleared either when the channel DMA transfer is done or by writing a 1 to CHnF bit.
31.4.10 Reset Overview
The TPM is reset whenever any chip reset occurs.
When the TPM exits from reset:
• the TPM counter and the prescaler counter are zero and are stopped (CMOD[1:0] =
0:0);
• the timer overflow interrupt is zero;
• the channels interrupts are zero;
• the channels are in input capture mode;
• the channels outputs are zero;
• the channels pins are not controlled by TPM (ELS(n)B:ELS(n)A = 0:0).
31.4.11 TPM Interrupts
This section describes TPM interrupts.
Chapter 31 Timer/PWM Module (TPM)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 571
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