32.3.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H)
This register is intended for applications that chain timer 0 and timer 1 to build a 64-bit
lifetimer.
Address: 4003_7000h base + E0h offset = 4003_70E0h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
LTH
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIT_LTMR64H field descriptions
Field Description
0–31
LTH
Life Timer value
Shows the timer value of timer 1. If this register is read at a time t1, LTMR64L shows the value of timer 0
at time t1.
32.3.3 PIT Lower Lifetime Timer Register (PIT_LTMR64L)
This register is intended for applications that chain timer 0 and timer 1 to build a 64-bit
lifetimer.
To use LTMR64H and LTMR64L, timer 0 and timer 1 need to be chained. To obtain the
correct value, first read LTMR64H and then LTMR64L. LTMR64H will have the value
of CVAL1 at the time of the first access, LTMR64L will have the value of CVAL0 at the
time of the first access, therefore the application does not need to worry about carry-over
effects of the running counter.
Address: 4003_7000h base + E4h offset = 4003_70E4h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
LTL
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIT_LTMR64L field descriptions
Field Description
0–31
LTL
Life Timer value
Shows the value of timer 0 at the time LTMR64H was last read. It will only update if LTMR64H is read.
Chapter 32 Periodic Interrupt Timer (PIT)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 577
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