NXP Semiconductors MKL25Z128VLK4 - Page 59

Low-Leakage Wake-up
Unit (LLWU)
Power Management
Controller (PMC)
Peripheral
bridge 0
Register
access
Wake-up
requests
Module
Module
Figure 3-7. Low-Leakage Wake-up Unit configuration
Table 3-14. Reference links to related information
Topic Related module Reference
Full description LLWU LLWU
System memory map System memory map
Clocking Clock distribution
Power management Power management chapter
Power Management
Controller (PMC)
Power Management Controller (PMC)
System Mode
Controller (SMC)
System Mode Controller
Wake-up requests LLWU wake-up sources
3.4.4.1 LLWU interrupt
NOTE
Do not mask the LLWU interrupt when in LLS mode. Masking
the interrupt prevents the device from exiting stop mode when a
wakeup is detected.
3.4.4.2 Wake-up Sources
The device uses the following internal peripheral and external pin inputs as wakeup
sources to the LLWU module. LLWU_Px are external pin inputs, and LLWU_M0IF-
M7IF are connections to the internal peripheral interrupt flags.
NOTE
In addition to the LLWU wakeup sources, the device also
wakes from low power modes when NMI or RESET pins are
enabled and the respective pin is asserted.
Chapter 3 Chip Configuration
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 59