Configure SPI before Transmission
RESET
Configure DMA Controller
for SPI transmission
Set SPE=1 to start transmission in
master mode or enable SPI for
transmission in slave mode
Wait for interrupt(s) of DMA Controller
indicating end of SPI transmission
Read SPI status register
Write the first byte to SPI data register
via CPU
Set TXDMAE to enable Transmit by
DMA
Figure 37-22. Recommended startup of SPI transmit by DMA
37.4.4.2 Receive by DMA
Receive by DMA is supported only when RXDMAE is set. A receive DMA request is
asserted when both SPE and SPRF are set. Then the on-chip DMA controller detects this
request and transfers data from the SPI data register into memory. After that, RX DMA
DONE is asserted to clear SPRF automatically. This process repeats until all data to be
received (the number is decided by configuration register[s] of the DMA controller) is
received or no receive DMA request is generated again because the SPI transmission is
finished.
37.4.5 SPI Clock Formats
To accommodate a wide variety of synchronous serial peripherals from different
manufacturers, the SPI system has a clock polarity (CPOL) bit and a clock phase (CPHA)
control bit to select one of four clock formats for data transfers. CPOL selectively inserts
an inverter in series with the clock. CPHA chooses between two different clock phase
relationships between the clock and data.
Chapter 37 Serial Peripheral Interface (SPI)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 673
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