NXP Semiconductors MKL25Z128VLK4 - Page 68

Table 3-22. Reference links to related information (continued)
Topic Related module Reference
Programming model System Integration
Module (SIM)
SIM
3.4.10.1 COP clocks
The two clock inputs for the COP are the 1 kHz clock and the bus clock.
3.4.10.2 COP watchdog operation
The COP watchdog is intended to force a system reset when the application software fails
to execute as expected. To prevent a system reset from the COP timer (when it is
enabled), application software must reset the COP counter periodically. If the application
program gets lost and fails to reset the COP counter before it times out, a system reset is
generated to force the system back to a known starting point.
After any reset, the COP watchdog is enabled. If the COP watchdog is not used in an
application, it can be disabled by clearing COPCTRL[COPT] in the SIM.
The COP counter is reset by writing 0x55 and 0xAA (in that order) to the address of the
SIM's Service COP (SRVCOP) register during the selected timeout period. Writes do not
affect the data in the SRVCOP register. As soon as the write sequence is complete, the
COP timeout period is restarted. If the program fails to perform this restart during the
timeout period, the microcontroller resets. Also, if any value other than 0x55 or 0xAA is
written to the SRVCOP register, the microcontroller immediately resets.
The SIM's COPCTRL[COPCLKS] field selects the clock source used for the COP timer.
The clock source options are either the bus clock or an internal 1 kHz clock source. With
each clock source, there are three associated timeouts controlled by COPCTRL[COPT].
The following table summarizes the control functions of the COPCLKS and COPT bits.
The COP watchdog defaults to operation from the 1 kHz clock source and the longest
timeout for that clock source (2
10
cycles).
Table 3-23. COP configuration options
Control Bits Clock Source COP Window Opens
(COPCTRL[COPW]=1)
COP Overflow Count
COPCTRL[COPCLKS] COPCTRL[COPT]
N/A 00 N/A N/A COP is disabled
0 01 1 kHz N/A 2
5
cycles (32 ms)
Table continues on the next page...
System Modules
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
68 Freescale Semiconductor, Inc.