NXP Semiconductors MKL25Z128VLK4 - Initialization;Application Information

37.4.11.5 Asynchronous interrupt in low power modes
When the CPU is in wait mode or stop mode and the SPI module receives a transmission,
the SPI module can generate an asynchronous interrupt to wake the CPU from the low
power mode. The module generates the asynchronous interrupt only when all of the
following conditions apply:
1. The C1[SPIE] bit is set to 1.
2. The CPU is in wait mode—in which case the C2[SPISWAI] bit must be 1—or in
stop mode where the peripheral bus clock is stopped but internal logic states are
retained.
3. The SPI module is in slave mode.
4. The received transmission ends.
After the interrupt wakes the CPU and the peripheral bus clock is active again, the SPI
module copies the received data from the shifter into the Data register and generates flags
or DMA request signals. During the wakeup phase, a continuous transmission from a
master would destroy the first received data.
37.5 Initialization/Application Information
This section discusses an example of how to initialize and use the SPI.
37.5.1 Initialization Sequence
Before the SPI module can be used for communication, an initialization procedure must
be carried out, as follows:
1. Update control register 1 (SPIx_C1) to enable the SPI and to control interrupt
enables. This register also sets the SPI as master or slave, determines clock phase and
polarity, and configures the main SPI options.
2. Update control register 2 (SPIx_C2) to enable additional SPI functions such as the
SPI match interrupt feature, the master mode-fault function, and bidirectional mode
output as well as to control and other optional features.
3. Update the baud rate register (SPIx_BR) to set the prescaler and bit rate divisor for
an SPI master.
4. Update the hardware match register (SPIx_M) with the value to be compared to the
receive data register for triggering an interrupt if hardware match interrupts are
enabled.
Chapter 37 Serial Peripheral Interface (SPI)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 683