40.3.1 Baud rate generation
As shown in the following figure, the clock source for the UART baud rate generator is
the bus-rate clock.
SBR[12:0]
Divide By
Tx Baud Rate
Rx Sampling Clock
(16 × Baud Rate)
Baud Rate Generator
Off If [SBR12:SBR0] = 0
Baud Rate =
SBR[12:0] × 16
16
Modulo Divide By
(1 through 8191)
UART Module Clock
UART Module Clock
Figure 40-30. UART baud rate generation
UART communications require the transmitter and receiver, which typically derive baud
rates from independent clock sources, to use the same baud rate. Allowed tolerance on
this baud frequency depends on the details of how the receiver synchronizes to the
leading edge of the start bit and how bit sampling is performed.
The MCU resynchronizes to bit boundaries on every high-to-low transition. In the worst
case, there are no such transitions in the full 10- or 11-bit or 12-bittime character frame
so any mismatch in baud rate is accumulated for the whole character time. For a
Freescale UART system whose bus frequency is driven by a crystal, the allowed baud
rate mismatch is about ±4.5 percent for 8-bit data format and about ±4 percent for 9-bit
data format. Although baud rate modulo divider settings do not always produce baud
rates that exactly match standard rates, it is normally possible to get within a few percent,
which is acceptable for reliable communications.
40.3.2 Transmitter functional description
This section describes the overall block diagram for the UART transmitter, as well as
specialized functions for sending break and idle characters.
The transmitter output (TxD) idle state defaults to logic high, UART_C3[TXINV] is
cleared following reset. The transmitter output is inverted by setting UART_C3[TXINV].
The transmitter is enabled by setting the TE bit in UARTxC2. This queues a preamble
character that is one full character frame of the idle state. The transmitter then remains
idle until data is available in the transmit data buffer. Programs store data into the
transmit data buffer by writing to the UART data register (UART_D).
The central element of the UART transmitter is the transmit shift register that is 10 or 11
or 12 bits long depending on the setting in the UART_C1[M] control bit and
UART_BDH[SBNS] bit. For the remainder of this section, assume UART_C1[M] is
Functional description
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
762 Freescale Semiconductor, Inc.
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