NXP Semiconductors MPC5566 - Development Control Registers 1 and 2 (DC1, DC2)

Nexus
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 25-37
25.11.2 Development Control Registers 1 and 2 (DC1, DC2)
The development control registers are used to control the basic development features of the NZ6C3
module. Development control register 1 is shown in Figure 25-15 and its fields are described in
Table 25-26.
Nexus Reg: 0x0002 Access: R/W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R OPC MCK_DIV
EOC
0
PTM WEN
00000000
W
Reset0000000000000000
1514131211109876543210
R
OVC EIC TM
W
Reset0000000000000000
Figure 25-15. Development Control Register 1 (DC1)
Table 25-26. DC1 Field Descriptions
Field Description
31
OPC
1
Output port mode control.
0 Reduced-port mode configuration (four MDO pins)
1 Full-port mode configuration (12 MDO pins)
30–29
MCK_DIV
[1:0]
1
MCKO clock divide ratio (refer to note below).
00 MCKO is 1x processor clock frequency.
01 MCKO is 1/2x processor clock frequency.
10 MCKO is 1/4x processor clock frequency.
11 MCKO is 1/8x processor clock frequency.
28–27
EOC[1:0]
EVTO
control.
00 EVTO
upon occurrence of watchpoints (configured in DC2)
01 EVTO upon entry into debug mode
10 EVTO upon time-stamping event
11 Reserved
26 Reserved
25
PTM
Program trace method.
0 Program trace uses traditional branch messages
1 Program trace uses branch history messages
24
WEN
Watchpoint trace enable.
0 Watchpoint Messaging disabled
1 Watchpoint Messaging enabled
23–8 Reserved
7–5
OVC[2:0]
Overrun control.
000 Generate overrun messages
001–010 Reserved
011 Delay processor for BTM / DTM / OTM overruns
1XX Reserved