Nexus
MPC5566 Microcontroller Reference Manual, Rev. 2
25-82 Freescale Semiconductor
25.17.2.8 Breakpoint/Watchpoint Address Registers 1 and 2 (BWA1 and BWA2)
The breakpoint/watchpoint address registers are compared with bus addresses to generate internal
watchpoints.
25.17.2.9 Unimplemented Registers
Unimplemented registers are those with client select and index value combinations other than those listed
in Table 25-46. For unimplemented registers, the NXDM module drives TDO to zero during the
“SHIFT-DR” state. It also transmits an error message with the invalid access opcode encoding.
25.17.2.10 Programming Considerations (RESET)
If Nexus3 register configuration is to occur during system reset (as opposed to debug mode), all NXDM
configuration should be completed between the negation of JCOMP and system reset de-assertion, after
the JTAG DID register has been read by the tool.
25.17.2.11 IEEE® 1149.1 (JTAG) Test Access Port
The NXDM module uses the IEEE® 1149.1 TAP controller for accessing Nexus resources. The JTAG
signals themselves are shared by all TAP controllers on the device. Refer to Chapter 24, “IEEE 1149.1 Test
Access Port Controller (JTAGC) for more information on the JTAG interface.
The NXDM modules implements a 4-bit instruction register (IR). The valid instructions and method for
register access are outlined in Section 25.7.2.3, “IEEE‚ 1149.1-2001 (JTAG) TAP.”
17–16
BWR2
Breakpoint/watchpoint #2 register compare
00 No register compare (same as BWC1[31:30] = 2’b00)
01 Reserved
10 Compare with BWA2 value
11 Reserved
15
BWT2
Breakpoint/watchpoint #2 Type
0Reserved
1 Watchpoint #2 on data accesses
14–0 Reserved, read as 0.
Access: R/W
313029282726252423222120191817161514131211109876543210
R
BREAKPOINT / WATCHPOINT ADDRESS
W
Reset00000000000000000000000000000000
Figure 25-63. Breakpoint / Watchpoint Address Registers (BWA1, BWA2)
Table 25-53. BWC2 Field Description (continued)
Field Description
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