MPC5566 Reference Manual Revision History
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor C-3
Chapter 5
“Peripheral Bridge”
Added footnote 2 to register figures 5-3 and 5-4 for the SP0 and TP0 bits:
The SP0 and TP0 bits default values are always used, even though the bits are writeable.
Added Notes to table 5-5 for the SP0 bit:
Note: For PBRIDGE_A_PACR0 and PBRIDGE_B_PACR0, you must have supervisor privileges to
access PBRIDGE registers.
Note: Even though the SP0 bit (1) is writeable, the reset value for SP0 is always used.
Added Notes to table 5-5 for the TP0 bit:
Note: For PBRIDGE_A_PACR0 and PBRIDGE_B_PACR0, you must have trusted master privileges
to access PBRIDGE registers.
Note: Even though the TP0 bit (1) is writeable, the reset value for TP0 is always used.
Added to Section 5.3.1.1Master Privilege Control Register: Although these registers are read/write,
the reserved fields shown do not apply to this device and must remain at the reset value, therefore
only write the fields’ reset value to the reserved fields of these registers. Also changed the read
value of the reserved fields to 0111.
Chapter 6
“System Integration Unit”
Added PCR71 TEA_GPIO.
Corrected the pin numbers in the PA tables for the following pad configuration registers (PCRs):
PCR57, PCR58, PCR59, PCR84, PCR95.
Corrected register addresses in register diagrams for the following PCRs: PCR122–PCR124,
PCR127–PCR133, PCR199–PCR200.
Reversed register addresses in register diagrams for PCR225–PCR220.
Chapter 7
“Crossbar Switch”
Added to Register Descriptions section: “Please note the difference in numerical values of XBAR
Master Port and Master ID as shown in Ta ble 7 -3 XBAR Switch Ports.”
Changed wording of reserved fields in registers:
From: “Reserved”
To: “Reserved, must be cleared.”
Ta bl e 7 -4 XBAR_MPRn Descriptions: Added text for MPR3 and MPR6 fields that all other values
than those stated are invalid. Changed ‘Reserved’ to ‘Invalid value”.
Figure 7-2 XBAR_MPRn Register: Made MPR3 (not included) and MPR6 (not included) fields
visible and read/write.
Ta bl e 7 -5 XBAR_SCPCRn Field Descriptions: Changed ‘Reserved’ values for the Park field to
‘Invalid value’.
Chapter 8
“Error Correction Status
Module”
• Added to section Initialization and Application, several paragraphs on precise exception
requirements.
• Added tables ‘Non-correctable Data ECC States’ and ‘MSR[EE] and MSR[ME] Bit Settings.
• Added footnote numeral 1 to the RESET rows of all figures that have undefined values upon
reset.
Changed Step 2 in the ECC procedure in Section 8.1.1 Overview to:
2. If the access is a write, then:
a. Merger new byte / halfword / word or doubleword into the 64 bits and calculate a
new ECC value.
b. Write the 64 bits and the ECC are to SRAM.
Section 8.3 Initialization and Application Information expanded to include exception processing.
Table C-1. MPC5566 Changes Between Revisions 1 and 2 (continued)
Chapter Description
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