NXP Semiconductors MPC5566 - Page 188

Reset
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 4-19
The following figure shows the process flow used for an internal reset:
Figure 4-6. Internal Reset Flow Diagram
False
True
False False
Assert
RSTOUT
Wait 2400
1
clock cycles
True True
Software
system reset
asserted
?
Internal
reset
asserted
?
Software
external reset
asserted
?
Assert internal
resets and
RSTOUT
A
Apply
WKPCFG pin
True
False
RSTCFG
asserted
?
Loss
of lock
negated
Default PLL
configuration
applied,
not latched
False
True
Wait 2400
1
clock cycles
Latch
WKPCFG pin
RSTCFG
asserted
?
Latch BOOTCFG
values
Wait four
clock cycles
Update reset
status register
Negate internal
resets &
RSTOUT
Latch default
boot configuration
False
True
Entry point from
external reset
flow and POR
False
True
Wait four
clock cycles
Latch PLLCFG
values
Latch default
PLL configuration
?
PLLCFG pins
applied,
not latched
Reset
request
negated
?
NOTES:
1
The clock count depends on the FMPLL configuration. Refer to Section 4.2.2, “Reset Output (RSTOUT).” If the
FMPLL is configure in dual controller (1:1) or bypass mode, the clock count is 16000.