NXP Semiconductors MPC5566 - Page 197

Peripheral Bridge (PBRIDGE A and PBRIDGE B)
MPC5566 Microcontroller Reference Manual, Rev. 2
5-8 Freescale Semiconductor
The type of peripheral designated by each PACR and OPACR access field is shown in Table 5-6.
Address: Base + 0x0020 (PBRIDGE_A_PACR0 and PBRIDGE_B_PACR0)
Base + 0x0028 (PBRIDGE_B_PACR2)
Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RBW0
1
SP0
2
WP0
TP0
2
BW1 SP1 WP1 TP1 BW2 SP2 WP2 TP2 BW3 SP3 WP3 TP3
W
Reset
A_PACR0
01
3
01
3
000000000000
Reset
B_PACR0
01
3
01
3
01
3
0000000000
Reset
B_PACR2
01
3
0001
3
0001
3
0001
3
00
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BW4 SP4 WP4 TP4 BW5 SP5 WP5 TP5 BW6 SP6 WP6 TP6 BW7 SP7 WP7 TP7
W
Reset
A_PACR0
0 000000000000000
Reset
B_PACR0
0 000000000000000
Reset
B_PACR2
0 000000000000000
1
In the PBRIDGE_A_PACR0 and PBRIDGE_B_PACR0 registers, the BW0 bit is not writeable.
2
The SP0 and TP0 bits default values are always used, even though the bits are writeable.
3
The default value is 0b0000 for PACR peripheral access fields that are unused or not connected.
Figure 5-3. Peripheral Access Control Registers (PBRIDGE_x_PACRn)
Access Field 0
Access Field 1
Access Field 2
Access Field 3
Access Field 4
Access Field 5
Access Field 6
Access Field 7