NXP Semiconductors MPC5566 - Page 312

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 6-109
The following register shows the location of the eQADC trigger input select fields:
The following table defines the values for the eQADC trigger input select fields:
Address: Base + 0x0900 Access: R/W
0123456789101112131415
R
TSEL5 TSEL4 TSEL3 TSEL2 TSEL1 TSEL0
0000
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000000000
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 6-161. eQADC Trigger Input Select Register (SIU_ETISR)
Table 6-150. SIU_ETISR Field Descriptions
Bits Name Description
0–1 TSEL5
[0:1]
eQADC trigger input select 5. Specifies the input for eQADC trigger 5.
00 GPIO[207]
01 ETPUA[26] channel
10 EMIOS[12] channel
11 ETRIG[1] pin
2–3 TSEL4
[0:1]
eQADC trigger input select 4. Specifies the input for eQADC trigger 4.
00 GPIO[206]
01 ETPUA[27] channel
10 EMIOS[13] channel
11 ETRIG[0] pin
4–5 TSEL3
[0:1]
eQADC trigger input select 3. Specifies the input for eQADC trigger 3.
00 GPIO[207]
01 ETPUA[28] channel
10 EMIOS[14] channel
11 ETRIG[1] pin
6–7 TSEL2
[0:1]
eQADC trigger input select 2. Specifies the input for eQADC trigger 2.
00 GPIO[206]
01 ETPUA[29] channel
10 EMIOS[15] channel
11 ETRIG[0] pin
8–9 TSEL1
[0:1]
eQADC trigger input select 1. Specifies the input for eQADC trigger 1.
00 GPIO[207]
01 ETPUA[31] channel
10 EMIOS[11] channel
11 ETRIG[1] pin