NXP Semiconductors MPC5606S - Destructive Event Status Register (RGM_DES)

Reset Generation Module (MC_RGM)
MPC5606S Microcontroller Reference Manual, Rev. 7
1078 Freescale Semiconductor
31.3.1.2 Destructive Event Status Register (RGM_DES)
This register contains the status of the last asserted destructive reset sources. It can be accessed in
read/write on either supervisor mode or test mode. Register bits are cleared on write 1.
NOTE
Clearing each flag in this register requires two clock cycles because of a
synchronization mechanism. As a consequence if a reset occurs while
clearing is on-going the reset may interrupt the clearing mechanism leaving
the flag set.
F_CHKSTOP Flag for checkstop reset
0 No checkstop reset event has occurred since either the last clear or the last power-on reset
1 A checkstop reset event has occurred
F_SOFT Flag for software reset
0 No software reset event has occurred since either the last clear or the last power-on reset
1 A software reset event has occurred
F_CORE Flag for core reset
0 No core reset event has occurred since either the last clear or the last power-on reset
1 A core reset event has occurred
F_JTAG Flag for JTAG initiated reset
0 No JTAG initiated reset event has occurred since either the last clear or the last power-on reset
1 A JTAG initiated reset event has occurred
Address 0xC3FE_4002 Access: Supervisor read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
F_POR
F_LVD27
F_SWT
F_LVD12_PD1 F_LVD12_PD0
W w1c w1c w1c w1c w1c
POR 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 31-3. Destructive Event Status Register (RGM_DES)
Table 31-3. Functional Event Status Register (RGM_FES) field descriptions (continued)
Field Description