NXP Semiconductors MPC5606S - SSD Prescale and Divider Register (PRESCALE)

Stepper Stall Detect (SSD)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1165
36.3.2.7 SSD Prescale and Divider Register (PRESCALE)
Figure 36-8 below describes the fields of the prescale and divider factor (PRESCALE) register:
The function of the PRESCALE register bits is shown in Table 36-9 below:
Offset 0x0C Access: User read/write
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BLNDIV
0
ITGDIV
0 0
OFFCNC
0
ACDIV
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 36-8. SSD Prescale and Divider Factor Register (PRESCALE)
Table 36-9. PRESCALE Register field description
Field Description
14–12
BLNDIV
Blanking Counter Clock Divider Select. The frequency for updating the down counter in the blanking
phase of the next BISs is derived from the bus clock according to the formula
<down counter clock> = <bus clock> / (8 * 2
BLNDIV
)
According to this formula the divider factors are:
000 8
001 16
010 32
011 64
100 128
101 256
110 512
111 1024
10–8
ITGDIV
Integration Counter Clock Divider Select. The frequency for updating the down counter in the
integration phase of the next BISs is derived from the bus clock according to the formula
<down counter clock> = <bus clock> / (8 * 2
ITGDIV
)
According to this formula the divider factors are:
000 8
001 16
010 32
011 64
100 128
101 256
110 512
111 1024
5–4
OFFCNC
Offset Cancellation polarity flip select. Refer to Section 36.4.1.4.3, DC Offset Cancellation, for details
of the offset cancellation mechanism. The OFFCNC bits set the preset value of the internal counter
which determines the polarity flips during the integration phase.
The preset value is derived from the ITGCNTLD register value with the following divider factor:
00 0: Selected polarity remains unchanged for all the time of the integration phase.
01 2: First polarity switch (and possibly a succeeding one) occurs after [ITGCNTLD div 2] DCNT
ticks.
10 4: First polarity switch and succeeding ones occur after [ITGCNTLD div 4] DCNT ticks.
11 8: First polarity switch and succeeding ones occur after [ITGCNTLD div 8] DCNT ticks.
If the ITGCNTLD register value cannot be divided by the required factor, an additional polarity flip
occurs with a duration corresponding to the bits shifted out.