System Timer Module (STM)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1225
Table 39-5. STM_CIRn field descriptions
39.3.2.5 STM Channel Compare Register (STM_CMPn)
The STM channel compare register (STM_CMPn) holds the compare value for channel n.
Table 39-6. STM_CMPn Register field descriptions
39.4 Functional description
The System Timer Module (STM) is a 32-bit timer designed to support commonly required system and
application software timing functions. The STM includes a 32-bit up counter and four 32-bit compare
channels with a separate interrupt source for each channel.
The STM has one 32-bit up counter (STM_CNT) that is used as the time base for all channels. When
enabled, the counter increments at the system clock frequency divided by a prescale value. The
STM_CR[CPS] field sets the divider to any value in the range from 1 to 256. The counter is enabled with
the STM_CR[TEN] bit. When enabled in normal mode the counter continuously increments. When the
MCU is stopped by a debugger, the counter operation is controlled by the STM_CR[FRZ] bit. When the
STM_CR[FRZ] bit is set, the counter is stopped in debug mode, otherwise it continues to run in debug
mode. The counter rolls over at 0xFFFF_FFFF to 0x0000_0000 with no restrictions at this boundary.
The STM has four identical compare channels. Each channel includes a channel control register
(STM_CCRn), a channel interrupt register (STM_CIRn) and a channel compare register (STM_CMPn).
The channel is enabled by setting the STM_CCRn[CEN] bit. When enabled, the channel will set the
STM_CIR[CIF] bit and generate an interrupt request when the channel compare register matches the timer
counter. The interrupt request is cleared by writing a 1 to the STM_CIRn[CIF] bit. A write of 0 to the
STM_CIRn[CIF] bit has no effect.
Field Description
CIF Channel Interrupt Flag
0 No interrupt request.
1 Interrupt request due to a match on the channel.
Offset 0x18+0x10*n Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CMP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 39-5. STM Channel Compare Register (STM_CMPn)
Field Description
CMP Compare value for channel n. If the STM_CCRn[CEN] bit is set and the STM_CMPn register matches the
STM_CNT register, a channel interrupt request is generated and the STM_CIRn[CIF] bit is set.
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