Revision History
MPC5606S Microcontroller Reference Manual, Rev. 7
1324 Freescale Semiconductor
Mode Entry Module
(MC_ME)
Corrected reset value of of Figure 25-17 (Peripheral Status Register 0 (ME_PS0)) to
0x0000_0000.
Corrected reset value of of Figure 25-18 (Peripheral Status Register 1 (ME_PS1)) to
0x0000_0000.
Corrected reset value of of Figure 25-19 (Peripheral Status Register 2 (ME_PS2)) to
0x0000_0000.
Corrected reset value of of Figure 25-20 (Peripheral Status Register 3 (ME_PS3)) to
0x0000_0000.
Corrected title of Table 25-12 (Peripheral Status Registers 0…3 (ME_PS0…3) field
descriptions) to reflect the correct number of ME_PSn registers (0:3).
Nexus Development
Interface (NDI)
Removed Doze mode references:
— In Tabl e 26-7 (DS field descriptions), changed value xx1 for LPS bit to reserved.
Quad Serial Peripheral
Interface (QuadSPI)
Removed Doze mode references:
— In Section 30.2.2, Features, removed bullet “Support for global signal Doze mode “
— In Section 30.5.1, Modes of operation, removed this phrase from the final bullet: “ or
when a request is asserted by an external controller while QSPI_MCR[DOZE] is set”
— In Figure 30-2 (Module Configuration Register (QSPI_MCR)), removed DOZE bit.
— In Tabl e 30-9 (QSPI_MCR field descriptions), removed DOZE bit.
— Removed Figure 577 (QuadSPI module with Power Management Block).
— In Section 30.2.3.4, Module Disable mode, removed bullet “The Module Disable mode
can also be initiated by hardware. A power management block can initiate Module
Disable mode by asserting the ipg_doze signal while the DOZE bit in the QSPI_MCR is
asserted.”
Sound Generation
Logic (SGL)
Changed the term “monotonic” to “monophonic.”
Updated Table 34-1 (Detailed signal descriptions), to clarify the description for the row
“pwm_ch0 to pwm_ch15.”
Added Table 34-4 (eMIOS channel mapping).
Stepper Stall Detect
(SSD)
Removed Doze mode references:
— Removed Section 36.1.3.3, Power Down modes as prefatory matter.
— Removed Section 36.1.3.3.1, Doze mode.
— Removed Section 36.1.3.3, Power Down modes as prefatory matter.
— Promoted Section 36.1.3.3.1, Doze mode by one heading level to Section 36.1.3.3,
Stop mode.
In Figure 36-2 (SSD Control and Status Register (CONTROL)), changed bit 0 to
reserved.
— In Tabl e 36-3 (CONTROL Register field description), changed bit 0 to reserved.
System Integration Unit
Lite (SIUL)
Added Notes to WPE bit in Table 37-10 (PCRx field descriptions):
[[[FSL_Specific]]] Note: When a pin is configured as an output, the weak internal pull
up/down is disabled regardless of the WPE or WPS settings in the PCR.
In Table 37-12 (Peripheral input pin selection), changed Peripheral input description for
PSMI[41] from I2C_RXD_1 to LINFLEX_RXD_1.
Appendix B,
Register Map
In Table B-2 (Detailed register map), added rows for PCR121–PCR132 and updated
memory space of subsequent reserved memory.
Table C-1. Changes between revisions 6 and 7 (continued)
Chapter Description
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