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NXP Semiconductors MPC5606S - Page 1342

NXP Semiconductors MPC5606S
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Revision History
MPC5606S Microcontroller Reference Manual, Rev. 7
1340 Freescale Semiconductor
Internal Static RAM Updated the column headings in the SRAM memory map table.
Memory Protection
Unit
In the overview, added the QuadSPI module to the list of slave ports.
Interrupt Controller Renumbered the eMIOS_GFR entries in the interrupt vector table.
In the “Interrupt Vector Table”, changed IRQs 67 and 87 to “Reserved”.
Flash Memory Replaced the “Platform Flash Controller” section.
Added the “Initialization/application information” section.
System Integration Unit
Lite
Corrected content throughout to reflect the fact that this device has 133 GPIO ports and is
not available in a 100-pin package.
Deleted the entry for PADSEL31 from the “Peripheral input pin selection” table.
Replaced the “Peripheral input pin selection” table.
Error Correction Status
Module
Added a note about bitwise operators to the “ECC Status Register (ESR)” section.
Revised the ESR figure.
Deleted the first paragraph in the “High Priority Enables” section.
System Timer Module Modified the structure of the chapter.
Deserial Serial
Peripheral Interface
Revised the list in the “Features” section.
Added information about the External Stop Mode.
Updated content throughout to reflect that this device has three chip selects and five FIFO
registers.
Changed the definition of DSPIx_MCR.
Added missing field DSPIx_CTARn field descriptions and associated tables.
Added information to the “Delay after Transfer” and “Continuous Serial Communications
Clock” sections.
Removed information relating to DSI and CSI modes.
Updated the “Continuous SCK Timing Diagram (CONT=1)” figure.
Added “with DBR = 0” to the first paragraph of the “Baud Rate Settings” section.
LIN Controller Replaced the entire chapter.
Added a note to the Introduction section indicating that only LINFlex_0 supports slave
mode.
FlexCAN Deleted the note in the “FlexCAN module features” section.
Deleted the note in the “FlexCAN memory mapping” section.
Deleted information about the Doze and Stop modes (not implemented on this device).
Deleted the MCR[SLF_WAK] field (is reserved).
Fixed the figure for the “Rx Individual Mask Registers”.
Deleted the note in the “Rx Individual Mask Registers” section.
Deleted the note in the “Matching Process” section.
Added information about MB grouping to the “Interrupts” section.
CAN Sampler Changed content throughout to reflect that Rx2–4 are present on this device.
Changed the contents of the “Internal multiplexer correspondence” table.
In the “Enabling/Disabling the CAN Sampler” section, added the text:
When the CAN sampler is enabled, the A, D, WEN, CSN and CK to the (12 x 32) block
of registers are switched to those generated by the kernel of the sampler. You can
monitor CR[Active_CK] to check which is the active clock to the registers.
Periodic Interrupt Timer Modified the structure of the chapter.
Table C-6. Changes between revisions 1 and 2 (continued)
Chapter Description

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