NXP Semiconductors MPC5606S - Channel Pending Registers (CEOCFR[1..2])

Analog-to-Digital Converter (ADC)
MPC5606S Microcontroller Reference Manual, Rev. 7
148 Freescale Semiconductor
5.4.3.2 Channel Pending Registers (CEOCFR[1..2])
The 0 to 31 range shown below is the maximum range for the channel type. For the exact number of
available channels, please refer to Table 5-5.
CEOCFR1 = End of conversion pending interrupt for channel 32 to 63 (extended internal channels)
CEOCFR2 = End of conversion pending interrupt for channel 64 to 95 (external channels)
29
JECH
End of Injected Chain Conversion interrupt (JECH) flag
It is the interrupt of the digital end of chain conversion for the injected channel; active when set. When
this bit is set, a JECH interrupt has occurred.
30
EOC
End of Channel Conversion interrupt (EOC) flag
It is the interrupt of the digital end of conversion. When this bit is set, an EOC interrupt has occurred.
31
ECH
End of Chain Conversion interrupt (ECH) flag
It is the interrupt of the digital end of chain conversion. When this bit is set, an ECH interrupt has
occurred.
Address: Base + 0x0018 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
EOC_CH63 EOC_CH62 EOC_CH61 EOC_CH60 EOC_CH59 EOC_CH58 EOC_CH57 EOC_CH56 EOC_CH55 EOC_CH54 EOC_CH53 EOC_CH52 EOC_CH51 EOC_CH50 EOC_CH49 EOC_CH48
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EOC_CH47 EOC_CH46 EOC_CH43 EOC_CH44 EOC_CH43 EOC_CH42 EOC_CH41 EOC_CH40 EOC_CH39 EOC_CH38 EOC_CH37 EOC_CH36 EOC_CH35 EOC_CH34 EOC_CH33 EOC_CH32
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-8. Channel Pending Register 1 (CEOCFR1)
Table 5-9. ISR field descriptions (continued)
Field Description