NXP Semiconductors MPC5606S - DMA Channel Select Register (DMAR[1..2])

Analog-to-Digital Converter (ADC)
MPC5606S Microcontroller Reference Manual, Rev. 7
154 Freescale Semiconductor
5.4.4.2 DMA Channel Select Register (DMAR[1..2])
The 0 to 31 range shown below is the maximum range for the channel type. For the exact number of
available channels, please refer to Table 5-5.
31DMAR1 = Enable bits for channels 32 to 63 (extended internal channels)
DMAR2 = Enable bits for channels 64 to 95 (external channels)
Reset value: 0x0000_0000
Address: Base + 0x0048 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
DMA
63
DMA
62
DMA
61
DMA
60
DMA
59
DMA
58
DMA
57
DMA
56
DMA
55
DMA
54
DMA
53
DMA
52
DMA
51
DMA
50
DMA
49
DMA
48
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
DMA
47
DMA
46
DMA
43
DMA
44
DMA
43
DMA
42
DMA
41
DMA
40
DMA
39
DMA
38
DMA
37
DMA
36
DMA
35
DMA
34
DMA
33
DMA
32
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-16. DMA Channel Select Register 1 (DMAR1)
Address: Base + 0x004C Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
DMA
95
DMA
94
DMA
93
DMA
92
DMA
91
DMA
90
DMA
89
DMA
88
DMA
87
DMA
86
DMA
85
DMA
84
DMA
83
DMA
82
DMA
81
DMA
80
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
DMA
79
DMA
78
DMA
77
DMA
76
DMA
75
DMA
74
DMA
73
DMA
72
DMA
71
DMA
70
DMA
69
DMA
68
DMA
67
DMA
66
DMA
65
DMA
64
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-17. DMA Channel Select Register 2 (DMAR2)
Table 5-16. DMARn field descriptions
Field Description
DMAn DMA enable
0 DMA transfer for channel n is disabled.
1 Channel n is enabled to transfer data in DMA mode.