NXP Semiconductors MPC5606S - Page 199

Clock Description
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 197
8.4.3.1.2 Output Clock Division Select Register (CGM_OCDS_SC)
This register is used to select the current output clock source and by which factor it is divided before being
delivered at the output clock.
Table 8-4. Output Clock Enable Register (CGM_OC_EN) field descriptions
Field Description
EN Output Clock Enable control
0 Output clock is disabled.
1 Output clock is enabled.
Address 0xC3FE_0374 Access: Supervisor read/write, User read-only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0
SELDIV
0
SELCTL
0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-4. Output Clock Division Select Register (CGM_OCDS_SC)
Table 8-5. Output Clock Division Select Register (CGM_OCDS_SC) field descriptions
Field Description
SELDIV Output Clock Division Select
00 Output selected: output clock without division.
01 Output selected: output clock divided by 2.
10 Output selected: output clock divided by 4.
11 Output selected: output clock divided by 8.
SELCTL Output Clock Source Selection Control — This value selects the current source for the output clock.
000 16 MHz internal RC oscillator
001 4–16 MHz external oscillator
010 Primary FMPLL
011 Secondary FMPLL
100 128 kHz internal RC oscillator
101 32 kHz external oscillator
110 reserved
111 reserved