NXP Semiconductors MPC5606S - Memory Map and Register Description

Clock Description
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 227
CMU_FDR. The frequency FRC can be derived from the value loaded in the CMU_FDR register as
follows:
FRC = (FOSC × MD) / n Eqn. 8-2
where n is the value in the CMU_FDR register and MD is the value in the CMU_MDR register.
By default, the frequency meter evaluates CK_FIRC, but the user can measure CK_SIRC or CK_SXOSC
by programming the CKSEL bits in CMU_CSR register. The CKON bits indicate which clock is at the
output of the multiplexer MUX1.
8.10.5 Memory map and register description
The memory map of the CMU is shown in the following table.
Table 8-27. RC Digital Interface Register Set — Base address 0xC3FE_0100
Register Name Address Offset Location
Control Status Register (CMU_CSR) 0x00 on page 228
Frequency Display Register (CMU_FDR) 0x04 on page 229
High Frequency Reference Register FMPLL0(CMU_HFREFR_A) 0x08 on page 229
Low Frequency Reference Register FMPLL0(CMU_LFREFR_A) 0x0C on page 230
Interrupt Status Register (CMU_ISR) 0x10 on page 230
Reserved 0x14 —
Measurement Duration Register (CMU_MDR) 0x18 on page 231
Address
Offset
Register
Name
0 1 2 3 4 5 6 7 8 9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
00
CMU_
CSR
Reserved
SFM
Reserved
CKSEL1
Reserved
RCDIV
CME
04
CMU_
FDR
Reserved FD[12:31]
08
CMU_
HFREFR
Reserved HFREF
0C
CMU_
LFREFR
Reserved LFREF
10 CMU_ISR Reserved
FHHI_A
FLLI_A
OLRI
14 Reserved Reserved
18
CMU_
MDR
Reserved MD[12:31]
Table 8-28. CMU register map