NXP Semiconductors MPC5606S - Page 317

Deserial Serial Peripheral Interface (DSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 315
Table 11-21 shows an example of the computed after SCK delay.
11.8.4.4 Delay after transfer (t
DT
)
The delay after transfer is the length of time between negation of the CSx signal for a frame and the
assertion of the CSx signal for the next frame. The PDT and DT fields in the DSPIx_CTARn registers
select the delay after transfer.
Refer to Figure 11-14 for an illustration of the delay after transfer.
The following formula expresses the PDT/DT/delay after transfer relationship:
Table 11-22 shows an example of the computed delay after transfer.
When in non-continuous clock mode the t
DT
delay is configurable as outlined in the DSPI_CTARx
registers. When in continuous clock mode and TSB is not enabled, the delay is fixed at 1 SCK period.
When in TSB and continuous mode the delay is programmed as outlined in the DSPI_CTARx registers,
but in the event that the delay does not coincide with an SCK period in duration, then the delay is extended
to the next SCK active edge. Table 11-23 shows an example of how to compute the delay after transfer
with the clock period of SCK defined as T
SCK
. The values calculated assume 1 TSCK period = 4 ipg_clk.
Table 11-21. After SCK delay computation example
PASC Prescaler value ASC Scaler value f
SYS
After SCK delay
0b01 3 0b0100 32 100 MHz 0.96 s
Table 11-22. Delay after transfer computation example
PDT Prescaler value DT Scaler value f
SYS
Delay after transfer
0b01 3 0b1110 32768 100 MHz 0.98 ms
t
DT
=
f
SYS
DT

PDT
1
