Deserial Serial Peripheral Interface (DSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
326 Freescale Semiconductor
11.8.7 Interrupts/DMA requests
The DSPI has five conditions that can generate interrupt requests only, and two conditions that can
generate interrupt.
Table 11-25 lists the seven conditions.
Each condition has a flag bit and a request enable bit. The flag bits are described in Section 11.7.2.4, DSPI
Status Register (DSPIx_SR), and the request enable bits are described in Section 11.7.2.5, DSPI DMA /
Interrupt Request Select and Enable Register (DSPIx_RSER). The TX FIFO fill flag (TFFF) and RX FIFO
drain flag (RFDF) generate interrupt requests or DMA requests, depending on the TFFF_DIRS and
RFDF_DIRS bits in the DSPIx_RSER.
11.8.7.1 End of queue interrupt request (EOQF)
The end of queue request indicates that the end of a transmit queue has been reached. The end of queue
request is generated when the EOQ bit in the executing SPI command is asserted and the EOQF_RE bit in
the DSPIx_RSER is set. Refer to the EOQ bit description in Section 11.7.2.4, DSPI Status Register
(DSPIx_SR). Refer to Figure 11-14 and Figure 11-15 that illustrate when EOQF is set.
11.8.7.2 Transmit FIFO fill interrupt or DMA request (TFFF)
The transmit FIFO fill request indicates that the TX FIFO is not full. The transmit FIFO fill request is
generated when the number of entries in the TX FIFO is less than the maximum number of possible entries,
and the TFFF_RE bit in the DSPIx_RSER is set. The TFFF_DIRS bit in the DSPIx_RSER selects whether
a DMA request or an interrupt request is generated.
11.8.7.3 Transfer complete interrupt request (TCF)
The transfer complete request indicates the end of the transfer of a serial frame. The transfer complete
request is generated at the end of each frame transfer when the TCF_RE bit is set in the DSPIx_RSER.
Refer to the TCF bit description in Section 11.7.2.4, DSPI Status Register (DSPIx_SR). Refer to
Figure 11-14 and Figure 11-15 that illustrate when TCF is set.
Table 11-25. Interrupt and DMA request conditions
Condition Flag Interrupt DMA
End of transfer queue has been reached (EOQ) EOQF X
TX FIFO is not full TFFF X X
Current frame transfer is complete TCF X
TX FIFO underflow has occurred TFUF X
RX FIFO is not empty RFDF X X
RX FIFO overflow occurred RFOF X
A FIFO overrun occurred
1
1
The FIFO overrun condition is created by ORing the TFUF and RFOF flags together.
TFUF ORed with RFOF X
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