NXP Semiconductors MPC5606S - Page 376

Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
374 Freescale Semiconductor
Figure 12-22. Interrupt Mask Register (INT_MASK)
Offset: 0x1F0 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0
M_P4_FIFO_HI_FLAG
M_P4_FIFO_LO_FLAG
M_P3_FIFO_HI_FLAG
M_P3_FIFO_LO_FLAG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0
M_DMA_TRANS_FINISH
0 0
M_IPM_ERROR
M_PROG_END
M_P2_FIFO_HI_FLAG
M_P2_FIFO_LO_FLAG
M_P1_FIFO_HI_FLAG
M_P1_FIFO_LO_FLAG
M_CRC_OVERFLOW
M_CRC_READY
M_VS_BLANK
M_LS_BF_VS
M_UNDRUN
M_VSYNC
W
Reset 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Table 12-24. INT_MASK field descriptions
Field Description
12
M_P4_FIFO_HI_FLAG
P4_FIFO_HI_FLAG interrupt mask
0 Interrupt is not masked
1 Interrupt is masked
13
M_P4_FIFO_LO_FLAG
P4_FIFO_LO_FLAG interrupt mask
0 Interrupt is not masked
1 Interrupt is masked
14
M_P3_FIFO_HI_FLAG
P3_FIFO_HI_FLAG interrupt mask
0 Interrupt is not masked
1 Interrupt is masked
15
M_P3_FIFO_LO_FLAG
P3_FIFO_LO_FLAG interrupt mask
0 Interrupt is not masked
1 Interrupt is masked
17
M_DMA_TRANS_FINISH
DMA_TRANS_FINISH interrupt mask
0 Interrupt is not masked
1 Interrupt is masked
20
M_IPM_ERROR
IPM_ERROR interrupt mask
0 Interrupt is not masked
1 Interrupt is masked