Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
494 Freescale Semiconductor
Figure 15-22. DMA General Purpose Output Register (DMAGPOR)
15.3.1.17 DMA Channel n Priority (DCHPRIn), n = 0,..., {15,31,63} registers
When the fixed-priority channel arbitration mode is enabled (DMACR[ERCA] = 0), the contents of these
registers define the unique priorities associated with each channel within a group. The channel priorities
are evaluated by numeric value — 0 is the lowest priority, 1 is the next higher priority, then 2, 3, etc.
Software must program the channel priorities with unique values, otherwise a configuration error will be
reported. The range of the priority value is limited to the values of 0–15. When read, the GRPPRI bits of
the DCHPRIn register reflect the current priority level of the group of channels in which the corresponding
channel resides. GRPPRI bits are not affected by writes to the DCHPRIn registers. The group priority is
assigned in the DMACR. See Figure 15-2 and Table 15-2 for the DMACR definition.
Channel preemption is enabled on a per channel basis by setting the ECP bit in the DCHPRIn register.
Channel preemption allows the executing channel’s data transfers to be temporarily suspended in favor of
starting a higher priority channel. After the preempting channel has completed all of its minor loop data
transfers, the preempted channel is restored and resumes execution. After the restored channel completes
one read/write sequence, it is again eligible for preemption. If any higher priority channel is requesting
service, the restored channel will be suspended and the higher priority channel will be serviced. Nested
preemption (attempting to preempt a preempting channel) is not supported. After a preempting channel
begins execution, it cannot be preempted. Preemption is only available when fixed arbitration is selected
for both group and channel arbitration modes.
A channel’s ability to preempt another channel can be disabled by setting the DPA bit in the DCHPRIn
register. When a channel’s preempt ability is disabled, that channel cannot suspend a lower priority
channel’s data transfer; regardless of the lower priority channel’s ECP setting. This allows for a pool of
low-priority, large data moving channels to be defined. These low-priority channels can be configured to
not preempt each other, thus preventing a low-priority channel from consuming the preempt slot normally
available to a true, high-priority channel. See
Figure 15-23 and Table 15-18 for the DCHPRIn definition.
Address: Base + 0x0038 Access: User read/write
R
GPOR[0:15]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
GPOR[16:31]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 15-17. DMA General Purpose Output Register (DMAGPOR) field descriptions
Name Description
GPOR[0:31] DMA General Purpose Output Register
The contents of this register is exported out of the DMA2.
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