NXP Semiconductors MPC5606S - Low;MID Address Space Block Locking Register (LML)

Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
560 Freescale Semiconductor
A number of MCR bits are protected against write when another bit, or set of bits, is in a specific state.
These write locks are covered on a bit by bit basis in the preceding description, but those locks do not
consider the effects of trying to write two or more bits simultaneously.
The flash module does not allow the user to write bits simultaneously which would put the device into an
illegal state. This is implemented through a priority mechanism among the bits. The bit changing priorities
are detailed in the following table.
If the user attempts to write two or more MCR bits simultaneously then only the bit with the lowest priority
level will be written.
17.2.6.2 Low/Mid Address Space Block Locking Register (LML)
Address Offset: 0x0004
Reset value: 0x00XXXXXX, initially determined by NVLML value from test sector.
Table 17-10. Low Address Space configuration
LAS2-0 Low Address Space Sectorization
000 Reserved
001 2128 KB
010 32 KB + 216 KB + 232 KB + 128 KB
011 Reserved
100 Reserved
101 Reserved
110 4 x 16KB
111 Reserved
Table 17-11. Mid Address Space configuration
MAS Mid Address Space Sectorization
0 2128 KB or 0 KB
1 Reserved
Table 17-12. MCR Bits Set/Clear Priority Levels
Priority Level MCR Bits
1 ERS
2 PGM
3 EHV
4 ESUS