FlexCAN
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 679
18.3.4 Register descriptions
The FlexCAN registers are described in this section in ascending address order.
18.3.4.1 Module Configuration Register (MCR)
This register defines global system configurations, such as the module operation mode (e.g., low-power)
and maximum message buffer configuration. Most of the fields in this register can be accessed at any time,
except the MAXMB field, which should only be changed while the module is in Freeze mode.
Table 18-7. Rx FIFO Structure field descriptions
Field Description
REM Remote Frame
This bit specifies if Remote frames are accepted into the FIFO if they match the target ID.
0 Remote frames are rejected and data frames can be accepted
1 Remote frames can be accepted and data frames are rejected
EXT Extended Frame
Specifies whether extended or standard frames are accepted into the FIFO if they match the target
ID.
0 Extended frames are rejected and standard frames can be accepted
1 Extended frames can be accepted and standard frames are rejected
RXIDA Rx Frame Identifier (Format A)
Specifies an ID to be used as acceptance criteria for the FIFO. In the standard frame format, only
the 11 most significant bits (3 to 13) are used for frame identification. In the extended frame format,
all bits are used.
RXIDB_0,
RXIDB_1
Rx Frame Identifier (Format B)
Specifies an ID to be used as acceptance criteria for the FIFO. In the standard frame format, the 11
most significant bits (a full standard ID) (3 to 13) are used for frame identification. In the extended
frame format, all 14 bits of the field are compared to the 14 most significant bits of the received ID.
RXIDC_0,
RXIDC_1,
RXIDC_2,
RXIDC_3
Rx Frame Identifier (Format C)
Specifies an ID to be used as acceptance criteria for the FIFO. In both standard and extended frame
formats, all 8 bits of the field are compared to the 8 most significant bits of the received ID.
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