NXP Semiconductors MPC5606S - Error and Status Register (ESR)

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MPC5606S Microcontroller Reference Manual, Rev. 7
690 Freescale Semiconductor
18.3.4.8 Error and Status Register (ESR)
This register reflects various conditions and some general status of the device, and it is the source of four
interrupts to the CPU. The reported error conditions (bits 16–21) are those that occurred since the last time
the CPU read this register. The CPU read action clears bits 16–21. Bits 22–28 are status bits.
Most bits in this register are read only, except TWRN_INT, RWRN_INT, BOFF_INT, and ERR_INT,
which are interrupt flags that can be cleared by writing 1 to them (writing 0 has no effect). See
Section 18.4.10, Interrupts, for more details.
Address: Base + 0x0020 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0
TWRN_INT
RWRN_INT
W w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BIT1_ ERR BIT0_ ERR
ACK_ ERR
CRC_ERR FRM_ERR
STF_ERR
TX_WRN
RX_WRN
IDLE
TXRX
FLT_CONF 0
BOFF_INT
ERR_ INT
WAK_INT
W w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 18-10. Error and Status Register (ESR)
Table 18-12. Error and Status Register (ESR) field descriptions
Field Description
TWRN_INT Tx Warning Interrupt Flag
If the WRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transitions
from 0 to 1, meaning that the Tx error counter has reached 96. If the corresponding mask bit in the
Control Register (TWRN_MSK) is set, an interrupt is generated to the CPU. This bit is cleared by
writing 1 to it. Writing 0 has no effect.
0 No such occurrence
1 The Tx error counter transitioned from < 96 to  96
RWRN_INT Rx Warning Interrupt Flag
If the WRN_EN bit in MCR is asserted, the RWRN_INT bit is set when the RX_WRN flag transitions
from 0 to 1, meaning that the Rx error counters reached 96. If the corresponding mask bit in the
Control Register (RWRN_MSK) is set, an interrupt is generated to the CPU. This bit is cleared by
writing 1 to it. Writing 0 has no effect.
0 No such occurrence
1 The Rx error counter transitioned from < 96 to  96