FlexCAN
MPC5606S Microcontroller Reference Manual, Rev. 7
692 Freescale Semiconductor
18.3.4.9 Interrupt Mask Register High (IMRH)
This register allows enabling or disabling any number of a range of 32 Message Buffer interrupts. It
contains one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an
interrupt after a successful transmission or reception (for example, when the corresponding IFRH bit is
set).
TXRX Current FlexCAN status (transmitting/receiving)
This bit indicates if FlexCAN is transmitting or receiving a message when the CAN bus is not in Idle
state. This bit has no meaning when IDLE is asserted.
0 FlexCAN is receiving a message (IDLE=0)
1 FlexCAN is transmitting a message (IDLE=0)
FLT_CONF Fault Confinement State
This 2-bit field indicates the Confinement State of the FlexCAN module, as shown in Table 18-13. If
the LOM bit in the Control Register is asserted, the FLT_CONF field will indicate the Error Passive
state. Since the Control Register is not affected by soft reset, the FLT_CONF field will not be
affected by soft reset if the LOM bit is asserted.
BOFF_INT Bus Off Interrupt
This bit is set when FlexCAN enters ‘Bus Off’ state. If the corresponding mask bit in the Control
Register (BOFF_MSK) is set, an interrupt is generated to the CPU. This bit is cleared by writing 1
to it. Writing 0 has no effect.
0 No such occurrence
1 FlexCAN module entered the Bus Off state
ERR_INT Error Interrupt
This bit indicates that at least one of the Error Bits (bits 16-21) is set. If the corresponding mask bit
in the Control Register (ERR_MSK) is set, an interrupt is generated to the CPU. This bit is cleared
by writing 1 to it. Writing 0 has no effect.
0 No such occurrence
1 Indicates setting of any Error Bit in the Error and Status Register
Table 18-13. Fault confinement state
Value Meaning
00 Error Active
01 Error Passive
1X Bus Off
Table 18-12. Error and Status Register (ESR) field descriptions (continued)
Field Description
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