NXP Semiconductors MPC5606S - Interrupt Mask Register Low (IMRL)

FlexCAN
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 693
18.3.4.10 Interrupt Mask Register Low (IMRL)
This register allows enabling or disabling any number of a range of 32 Message Buffer interrupts. It
contains one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an
interrupt after a successful transmission or reception (for example, when the corresponding IFRL bit is
set).
Base + 0x0024
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
BUF
63M
BUF
62M
BUF
61M
BUF
60M
BUF
59M
BUF
58M
BUF
57M
BUF
56M
BUF
55M
BUF
54M
BUF
53M
BUF
52M
BUF
51M
BUF
50M
BUF
49M
BUF
48M
W
RESET:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BUF
47M
BUF
46M
BUF
45M
BUF
44M
BUF
43M
BUF
42M
BUF
41M
BUF
40M
BUF
39M
BUF
38M
BUF
37M
BUF
36M
BUF
35M
BUF
34M
BUF
33M
BUF
32M
W
RESET:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 18-11. Interrupt Mask Register High (IMRH)
Table 18-14. IMRH field descriptions
Field Description
BUF63M –
BUF32M
Buffer MB
i
Mask
Each bit enables or disables the respective FlexCAN Message Buffer (MB32 to MB63) interrupt.
0 The corresponding buffer interrupt is disabled
1 The corresponding buffer interrupt is enabled
Note: Setting or clearing a bit in the IMRH register can assert or negate an interrupt request, if the
corresponding IFRH bit is set.
Address: Base + 0x0028 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
BUF 31M BUF 30M BUF 29M BUF 28M BUF 27M BUF 26M BUF 25M BUF 24M BUF 23M BUF 22M BUF 21M BUF 20M BUF 19M BUF 18M BUF 17M BUF 16M
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BUF 15M BUF 14M BUF 13M BUF 12M BUF 11M BUF 10M
BUF 9M BUF 8M BUF 7M BUF 6M BUF 5M BUF 4M BUF 3M BUF 2M BUF 1M BUF 0M
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 18-12. Interrupt Mask Register Low (IMRL)